The present invention relates generally to integrated circuits (ICs) and methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing integrated circuits having transistors with specialized gate conductors.
Integrated circuits (ICs), such as, ultra-large-scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). The transistors often include semiconductor or metal gates disposed above a channel region and between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The semiconductive gates are conventionally manufactured from metal material or amorphous and polycrystalline material. For example, polysilicon and polysilicon/germanium gate conductors can be utilized. The polysilicon gate conductors are deposited as polysilicon material by chemical vapor deposition (CVD). The polysilicon material is generally heavily doped with P-type or N-type dopants to increase conductivity and thereafter annealed in a high temperature process to activate the dopants.
Although polysilicon gate conductors are heavily doped, gate resistance in polysilicon gate conductors can be problematic. For example, as gate conductors are reduced in size, the cross-sectional dimensions are also reduced. As gate widths become smaller, the cross sectional width of the gate conductor becomes smaller. As the thickness of the layers becomes smaller, the height of the gate conductors is also decreased. Therefore, a reduction in size of the gate conductor reduces the cross sectional area of the conductor. A reduction in cross sectional dimensions increases the resistive characteristics of the gate conductor (e.g., sheet resistance).
As the physical dimensions of CMOS transistors are decreased, control of critical dimensions (CD) associated with the gate conductor becomes more difficult. For example, as critical dimensions associated with the gate conductor (e.g., gate length) reach the nanometer dimensions, the grain structure of the polysilicon material can affect the accuracy of the gate formation process. More particularly, edge roughness due to the grain size variation in the polysilicon material can change or vary the gate length (along the width) of the transistor. This variation in gate length makes the transistor susceptible to short channel effects. Short channel effects can disadvantageously increase the leakage or off-current when the transistor is not turned on.
As critical dimensions are reduced, IC fabrication processes can manufacture specialized devices, such as, resonant tunneling transistors (RTT) which have CDs in the nanometer range. RTTs can include resonant hot-electron transistor (RHET), quantum excited state transistors (qUEST) and other configurations. These transistors are particularly susceptible to grain structure difficulties associated with polysilicon gate material.
In addition, resonant tunneling devices are easier to manufacture if high quality thermal oxide materials can be formed on the gate. Generally, polysilicon materials cannot be utilized to produce high quality thermal oxide materials.
Thus, there is a need for an integrated circuit or electronic device that includes gate conductors manufactured from a material that can be accurately patterned. Further still, there is a need for transistors with a gate conductor that are not susceptible to size variation due to granularity. Even further still, there is a need for a resonant tunneling transistor (RTT) having a specialized gate conductor. Yet even further, there is a need for a low resistance gate conductor and a method of manufacturing such a conductor.
An exemplary embodiment relates to a method of manufacturing an integrated circuit on a substrate. The method includes providing a first semiconductor layer above a surface of the substrate, patterning the first semiconductor layer to form a first gate conductor layer, utilizing solid phase epitaxy to form a single crystal layer above the first gate conductor, and patterning the single crystal layer to form a second gate conductor layer including the single crystal layer.
Another exemplary embodiment relates to a method of fabricating a transistor. The transistor includes a gate conductor comprised of single crystal silicon material. The method includes steps of providing a first thin polysilicon layer, providing a single crystal layer over the thin polysilicon layer, and patterning the single crystalline layer to form the gate conductor including the single crystal silicon material.
Yet another exemplary embodiment relates to a process of forming a transistor having a single crystal material in a gate structure. The gate structure is above a top surface of a substrate. The process includes providing a dielectric layer above a top surface of the substrate, forming a thin gate conductor layer above the dielectric layer, and etching the dielectric layer and the thin gate conductor layer to expose to the top surface of the substrate. The method further includes forming a crystallized layer over the thin gate conductor layer and etching portions of the crystallized layer to form the gate structure.